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[VHDL-FPGA-Verilog] 异步FIFO存储器的控制设计

Description: 异步FIFO控制器的设计 主要用于异步先进先出控制器的设计。 所用语言Verilog HDL.-asynchronous FIFO controller design for the main asynchronous FIFO controller design. The language used Verilog HDL.
Platform: | Size: 6144 | Author: 李鹏 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 异步FIFO控制器的Verilog设计与实现-Asynchronous FIFO controller Verilog Design and Implementation
Platform: | Size: 5120 | Author: 陈晨 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 异步FIFO verilog实现 异步FIFO verilog实现 -Asynchronous FIFO verilog realize realize asynchronous FIFO verilog
Platform: | Size: 4096 | Author: lyjIC | Hits:

[Software Engineering] Asyn_FIFO_Design

Description: 异步FIFO设计的说明文档，需要注意的问题以及源码（在文中有）。是标准的异步FIFO，可综合。-Asynchronous FIFO design documentation, as well as the need to pay attention to source code (in the text have). Is a standard asynchronous FIFO, can be integrated.
Platform: | Size: 228352 | Author: 刘强 | Hits:

[VHDL-FPGA-Verilog] fifo-1117

Description: 这是异步FIFO的VHDL实现代码，已经在FPGA上通过实践证明，运行状态良好-This is the asynchronous FIFO realize the VHDL code, the FPGA has been proved through practice, running in good condition
Platform: | Size: 20480 | Author: 杨宇 | Hits:

[OS Develop] FIFO

Description: 一个异步的FIFO的VERILOG程序,有测试程序-An asynchronous FIFO in Verilog procedures, test procedures have
Platform: | Size: 4096 | Author: 陈强 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 使用VHDL编程的异步FIFO程序 经调试可运行-Using VHDL programming asynchronous FIFO procedure can be run by the debugger
Platform: | Size: 131072 | Author: 张星 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 用双端口ram实现异步fifo，采用格雷码，避免产生毛刺。-Using dual-port ram realize asynchronous fifo, the use of Gray code, avoiding the production of burr.
Platform: | Size: 1024 | Author: shili | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 异步FIFO的实现，可综合，可验证] keywords:almost_full,full,almost_empty,empty-The realization of asynchronous FIFO can be comprehensive, verifiable] keywords: almost_full, full, almost_empty, empty
Platform: | Size: 1024 | Author: ly | Hits:

[OS Develop] asyn_fifo

Description: verilog编写的异步fifo源代码，asyn_fifo.v为顶层，调用其他四个文件-asynchronous fifo prepared Verilog source code, asyn_fifo.v for top-level, call the other four documents
Platform: | Size: 2048 | Author: nihao | Hits:

[VHDL-FPGA-Verilog] fpga.fifo

Description: 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the phase and frequency offset between different clock domain in communication area .In this paper, an FIFO module is designed using Gray convert technology and dual-port ram , which realizing scatheless transmit between different clock domain. The advances of Gray (Only one bit changes between neighboring two clock ) improves the reliability and anti-jamming capability of the system. And the system can work normally in the bad condition which the phase and frequency offset target to 300PPM. It is proved by work that the FIFO module can fulfill the demands of real-time of data transmitting system, and the module is powerful enough for more data process in the future.
Platform: | Size: 81920 | Author: 雷志 | Hits:

[VHDL-FPGA-Verilog] fifo1

Description: 异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been
Platform: | Size: 32768 | Author: 何勇 | Hits:

[VHDL-FPGA-Verilog] FIFO_Design

Description: 一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码-Gray-code based on the Asynchronous FIFO Design and Implementation
Platform: | Size: 90112 | Author: qwe | Hits:

[Software Engineering] CummingsSNUG2002SJ_FIFO2

Description: Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons
Platform: | Size: 101376 | Author: sumit | Hits:

[VHDL-FPGA-Verilog] ASYNCFIFO

Description: 异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现-asynchronous fifo
Platform: | Size: 75776 | Author: Denny | Hits:

[Software Engineering] fifo

Description: 异步fifo的经典讲解，包括亚稳态的产生，同步电路的构造，fifo电路的结构，源代码实现。-Asynchronous fifo on the classic, including the emergence of metastable, the structure of synchronous circuits, fifo circuit structure, the source code to achieve.
Platform: | Size: 3224576 | Author: 王玉 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: Asynchronous FIFO source code
Platform: | Size: 364544 | Author: hr | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 同步和异步FIFO，VHDL实现。希望对大家有所帮助。-Synchronous and asynchronous FIFO, VHDL implementation. We want to help.
Platform: | Size: 589824 | Author: Jun | Hits:

[VHDL-FPGA-Verilog] async-FIFO

Description: 采用VHDL实现异步的FIFO程序，是学习FPGA的重点内容-VHDL implementation using asynchronous FIFO procedures, the key elements to learn FPGA! !
Platform: | Size: 220160 | Author: yihoumei | Hits:

[VHDL-FPGA-Verilog] fifo.vhdl

Description: 异步fifo的vhdl源代码,可实现异步信号的传送-The asynchronous fifo vhdl source code, enabling the transmission of asynchronous signals
Platform: | Size: 9216 | Author: 高丽 | Hits:
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